


module Biestable_reset_enable (clk,rst, q, d,we);
input clk,d,rst,we;
output q;
reg q;

always @ (posedge clk)
begin
	if (rst == 1)
	begin
		 q <= 0;
	end
	else 
	if(we==1)
	begin
		q <= d;
	end
end


endmodule


module Flip_flop_enable14 (clk, q, d,we);
input [13:0]d;
input  we,clk;
output [13:0] q;
reg [13:0]q;
always @(posedge clk)
 begin
	if(we==1)
	begin
		q <= d;
	end

end
endmodule

module Flip_flop_enable33 (clk, q, d,we);
input [32:0]d;
input  we,clk;
output [32:0] q;
reg [32:0]q;
always @(posedge clk)
 begin
	if(we==1)
	begin
		q <= d;
	end

end
endmodule

module Flip_flop_reset (q, data_in, clk, rst);
input [15:0]data_in;
input clk, rst;
output [15:0] q;
reg [15:0]q;
always @ (posedge clk)
begin
	if (rst == 1)
	begin
		 q <= 0;
	end
	else 
	begin
		q <= data_in;
	end
end

endmodule

module Flip_flop_reset_enable (q, data_in, clk, rst,we);
input [15:0]data_in;
input clk, rst,we;
output [15:0] q;
reg [15:0]q;
always @ (posedge clk)
begin
	if (rst == 1)
	begin
		 q <= 0;
	end
	else 
	if(we==1)
	begin
		q <= data_in;
	end
end
endmodule

module Flip_flop_reset_enable14 (clk,q, data_in,we,rst);
input [13:0]data_in;
input clk, rst,we;
output [13:0] q;
reg [13:0]q;
always @ (posedge clk)
begin
	if (rst == 1)
	begin
		 q <= 0;
	end
	else 
	if(we==1)
	begin
		q <= data_in;
	end
end
endmodule  

module Flip_flop_reset_enable33(clk,q, data_in,we,rst);
input [32:0]data_in;
input clk, rst,we;
output [32:0] q;
reg [32:0]q;
always @ (posedge clk)
begin
	if (rst == 1)
	begin
		 q <= 0;
	end
	else 
	if(we==1)
	begin
		q <= data_in;
	end
end
endmodule


